For anyone interested, I built this initially in falstad.com's circuit simulator (http://www.falstad.com/circuit/) since it's easy to share and less esoteric for others than LTSPICE or similar. He also has android and iOS versions available.
That's also why I consider it an "easy" design, because I can make something like this in a few minutes in a simulator it's just a matter of translating the circuit to redstone. Trying to design directly with redstone would be much harder, so don't do that.
$ 1 5.0E-6 10.20027730826997 50 5.0 50
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o 128 64 0 34 5.0 9.765625E-5 0 -1
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Yep. Redstone is similar to, but very different from, digital logic in electronics.
There are only 2 "voltage" states, on and off.
There is no concept of current.
There's no resistance, capacitance, or inductance.
Everyone calls SR latches RS latches. I'm not sure why, though it makes no real difference.
So any circuit that would use an op-amp can't be made. No 555-timers for redstone!
But it's turing complete, so you could, say, create 8-bit registers and simulate the operation of a 555 with 256 values representing 256 levels of voltage and current.
The ones I'd really like to see would be the wiring/redstone specific tutorials. Partly because I already know plenty of digital logic and circuit design (computer/electrical engineering does need that stuff) and partly because the non-redstone specific stuff is generally pretty well covered in tutorials elsewhere.
Most of my redstone problems are of the "Damnit, no insulation!" or the "How the hell do I make a filter without resistors, capacitors, inductors, or op-amps?" sort.
So I wanted to make a cryptographically-secure PRBG in Minecraft. I'm a total redstone noob*, only had the game for about 2-3 weeks, so a nice simple project that won't take more than a few hours seemed good, and no one seems to have made such a beast before.
First, a caveat: The generator I made is vulnerable to timing attacks, and the internal state is obviously visible. If you were going to actually use this you'd have to hide the innards, and also use a large buffer for the output. I've already spent about 6.5 hours on this, and covering it would prevent taking pictures, so I left that out. Making a buffer is pretty easy to do though, there's a single DFF for buffer but it's nowhere near enough.
It's certaily possible to make this smaller. Being new to redstone and its assosciated weirdness (no insulation!) I chose to make it big to prevent errors. I didn't use locked repeaters because they're currently (1.4.2) buggy and don't work for shift registers properly.
The generator I made is a type of CSPRBG called a "Self-Shrinking Generator". The basic design is as follows:
Start with a Linear Feedback Shift Register.
Clock 2 bits from the LFSR.
If the first bit is 1 and the second 0, output 0.
If the first bit is 1 and the second 1, output 1.
Otherwise, output nothing.
Clock 2 bits from the LFSR.... etc, etc.
To differentiate between outputing 0 and outputing nothing I just have an output clock that only pulses when output is actually present.
To start with I used Sethbling's pseudorandom pulse generators into an OR to allow for easy seeding/reseeding of the LFSR. A simple switch lets one turn this on and off.
There's also a manual input, for testing and adding one's own seeds.
A basic clock and pulse limiter (for use with low clock rates) into the LFSR.
The 32-bit LFSR is based off of CrucialCraft's 16-bit design. I'd tried a version using 1-wide tileable DFFs but it was too hard to get the shifting to work (damn no insulation!) so I used the spaced out version.
The primitive polynomial I used is 1 + x^23 + x^29 + x^30 + x^32, so the taps are at 32, 30, 29, and 23 (the 23-tap is a bit hidden in the pic, sorry. It's the same as the others.)
The last bit of the LFSR gets output into the self-shrinking section, but 2 bits need to be captured, so I run a clock at half the original clock rate, then use that clock and its negation into a pair of DFFs to store the pair of bits. The S bit runs a switch (NPN transistor via piston and redstone) and the output clock, and the A bit is the output (when the S is 1) .
The clock:
Rising edge detectors to clock the DFFs:
Overhead view of the DFFs and the switch:
And the actual outputs, also shows the final buffer DFF:
0
That's also why I consider it an "easy" design, because I can make something like this in a few minutes in a simulator it's just a matter of translating the circuit to redstone. Trying to design directly with redstone would be much harder, so don't do that.
0
There are only 2 "voltage" states, on and off.
There is no concept of current.
There's no resistance, capacitance, or inductance.
Everyone calls SR latches RS latches. I'm not sure why, though it makes no real difference.
So any circuit that would use an op-amp can't be made. No 555-timers for redstone!
But it's turing complete, so you could, say, create 8-bit registers and simulate the operation of a 555 with 256 values representing 256 levels of voltage and current.
0
Most of my redstone problems are of the "Damnit, no insulation!" or the "How the hell do I make a filter without resistors, capacitors, inductors, or op-amps?" sort.
0
First, a caveat: The generator I made is vulnerable to timing attacks, and the internal state is obviously visible. If you were going to actually use this you'd have to hide the innards, and also use a large buffer for the output. I've already spent about 6.5 hours on this, and covering it would prevent taking pictures, so I left that out. Making a buffer is pretty easy to do though, there's a single DFF for buffer but it's nowhere near enough.
It's certaily possible to make this smaller. Being new to redstone and its assosciated weirdness (no insulation!) I chose to make it big to prevent errors. I didn't use locked repeaters because they're currently (1.4.2) buggy and don't work for shift registers properly.
The generator I made is a type of CSPRBG called a "Self-Shrinking Generator". The basic design is as follows:
Start with a Linear Feedback Shift Register.
Clock 2 bits from the LFSR.
If the first bit is 1 and the second 0, output 0.
If the first bit is 1 and the second 1, output 1.
Otherwise, output nothing.
Clock 2 bits from the LFSR.... etc, etc.
To differentiate between outputing 0 and outputing nothing I just have an output clock that only pulses when output is actually present.
To start with I used Sethbling's pseudorandom pulse generators into an OR to allow for easy seeding/reseeding of the LFSR. A simple switch lets one turn this on and off.
There's also a manual input, for testing and adding one's own seeds.
A basic clock and pulse limiter (for use with low clock rates) into the LFSR.
The 32-bit LFSR is based off of CrucialCraft's 16-bit design. I'd tried a version using 1-wide tileable DFFs but it was too hard to get the shifting to work (damn no insulation!) so I used the spaced out version.
The primitive polynomial I used is 1 + x^23 + x^29 + x^30 + x^32, so the taps are at 32, 30, 29, and 23 (the 23-tap is a bit hidden in the pic, sorry. It's the same as the others.)
The last bit of the LFSR gets output into the self-shrinking section, but 2 bits need to be captured, so I run a clock at half the original clock rate, then use that clock and its negation into a pair of DFFs to store the pair of bits. The S bit runs a switch (NPN transistor via piston and redstone) and the output clock, and the A bit is the output (when the S is 1) .
The clock:
Rising edge detectors to clock the DFFs:
Overhead view of the DFFs and the switch:
And the actual outputs, also shows the final buffer DFF:
Imgur Album: http://imgur.com/a/xajEL
Overall it was a fun project, not terribly advanced but that's fine for a beginner* like me.
*New to redstone. Not new to digital logic & circuit design.