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# Modular/Expandable any-bit binary to BCD converter

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### #1

icks

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Posted 22 July 2011 - 10:58 PM

My implementation of the Double Dabble AKA shift/+3 algorithm for converting binary numbers to Binary Coded Decimal (BCD) as described here.

Sequential logic version:

The version is mostly for the visualisation of the algorithm so included are synced displays.

This video shows a 6 RT/operation version:

The world save contains a 4 RT/operation  version.
World Save: http://www.mediafire...kfwcqueoxct0szq

Block diagram:

Generic display: http://i.imgur.com/EpE9A.png
Shift/+3 modules: http://i.imgur.com/t7Izo.png
Inline 2RT sync-ed 4bit-7Segment: http://i.imgur.com/0saUS.png
Input "PISO": http://i.imgur.com/bQYbn.png

Instead of using whole PISO shift registers they have been stripped right down to a series of torch repeaters. The whole thing is unclocked and operates synchronously so the delay is set appropriately. Each operation takes 5RT and n-1 operations are needed in total, where n = No. of bits. For 16 bits, this is 75 RT. The set of D Flops are used to store the register value after the delay. During conversion they are transparent.

Each module is directly tilable/expandable to the left  for more digits and the input "PISO" expandable to the right for more bits except for the parts in yellow. These parts are used to keep the output synced. The ground level repeaters have an increase of 1RT setting from 0 to x  from left to right, where x = No. of digits - 1. The repeater circled in yellow should have a delay set equivalent to the ground level repeaters for the rightmost module i.e 4. Other than that copy/paste as needed. Or cut if you need less.

e.g For 10 bits
1. Take off 1 module from th right; the maximium needed to be displayed is 1023. Unless you want to display a leading 0....?
2. Take off 6 units on the input "PISO"
3. Adjust the delay to 5(10-1) = 45
3. Adjust/Remove repeaters on ground layer in yellow section to 0,1,2,3 from left to right for each module.
4. Adjust repeater circled in yellow to 3.

Combinational/Combinatorial version:

This version uses steady state logic 2/ticks per bit. The total delay is 2*(no. of bits - 3). Each module is 19 high, 8 wide (1 input every other block), and 6 deep (the important length) tileable.

16 bit version:

Schematic: http://www.mediafire...rv46ofsizg44qfd
Single module schematic: http://www.mediafire...j4n3ftdns84ojkw

### #2

DaftasBrush

Posted 23 July 2011 - 09:21 AM

OK.. well that answers my question from the other thread.. ( "Did you get it fixed?" )

Awesome!

and 5-ticks / op you say...?   This I gotta see..

### #3

icks

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Posted 23 July 2011 - 11:05 AM

Yeah i did. It can still sometimes not correctly display the right value but this is more do with storing the value in the D flops rather than the shift/+3 modules themselves stemming from torch randommess. I was working on trying to reduce that but was forced to release early....

If you find it more stable, the repeaters on the 3rd layer in the yellow section leading to the D flops should really be set to 2 so they can store the register value somewhere in the middle of a cycle. Or that is the theory. It seems to have worked better for me at 1.

### #4

ki113d

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Posted 23 July 2011 - 11:26 AM

Nice job icks, once again you have astounded me

### #5

Grizdale

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Posted 23 July 2011 - 03:53 PM

So what is the maximum delay this would take to compute?

### #6

icks

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Posted 23 July 2011 - 04:34 PM

Oh right, i'm sure i typed that.

In entirety, it's 5(n-1) where n = No. of bits to calculate, +1/module to sync, and a base delay of 3 ticks for the D flops to store. Display and decoding of the BCD i leave up to the user.

### #7

Jazza_Hat

Posted 07 December 2011 - 09:48 AM

Is it possible for you to upload the world again? It says it has been removed, thanks
Jazza

### #8

icks

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Posted 07 December 2011 - 05:55 PM

Sorry i cannot.

I don't have backups of many things and lost quite a bit of my Minecraft work a while ago. However, if you still wish to have it, a 4 tick version is on the RDF server with added two's complement support. It is on my plot which still should be labelled SW90 i think. Additionally if you ask around, someone on the server has one using the same circutry, equally as fast but fully tiled rather than a tiled/modular mix. I forget that person's name so very sorry to whomever that person is.

If CXGamer reads this maybe i can ask him to pull a schematic out for me/us?

### #9

Jazza_Hat

Posted 10 December 2011 - 09:07 AM

Good news, Shrogg found it! I'm currently studying it and building my own. If You want I can post the schematic for you?

### #10

icks

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Posted 10 December 2011 - 04:14 PM

Super!

I'm not active, but i like to keep what i have made working so i'd be very grateful for the schematic. Many thanks also to shrogg.

### #11

Jazza_Hat

Posted 11 December 2011 - 04:13 AM

There you go: http://www.mediafire...gd4w9v18f21usj0

I noticed an error with some repeaters on the far end of each unit.

### #12

No1Creeper

Posted 24 March 2012 - 02:25 AM

It appears the download link is broken could you consider re-uploading? this is by far the best binary to bcd decoder i've seen anywhere an i'd love to learn from it

### #13

icks

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Posted 24 March 2012 - 03:23 AM

You can try this: http://www.mediafire...3nrb48m8xkh0ro3 Built in 1.7 i think. I don't think it has a 2's complement converter attached to the input which i remember i added in a latter iteration. To be honest with you, it's a little archaic. Half a year later, everyone and their mother has built one, but most of them i have seen uses the same logic as this, so i guess it's still useful for that.